Asynchronous design methodologies are used to create high-performance, low-power circuit topologies. For instance, asynchronous controllers based on reactive sequential controllers only clock the datapath when new data tokens are present. The power consumption and/or performance of such circuits can be significantly improved by correctly sizing circuit elements through timing driven optimization processes. Such optimization processes are particularly effective for asynchronous controllers since the controller is used as a local timing reference to determine the frequency of the design; for example, the controller produces the high-power clock signal that drives components of the data path for bundled data asynchronous controller designs (e.g., latches, flip flops, and so on).
The sequential controllers described above include cyclic timing paths (referred to generally as “cycles”). As used herein, a “cycle” refers to any circuit topology in which a circuit element has an input that is formed from one or more circuit outputs. A cycle may comprise any number of intervening circuit elements, including, but not limited to: transistors, gates, latches, signal paths, buffers, and so on.
Circuit designs comprising cycles, such as the sequential controllers described above, may be generated using conventional circuit design tools, such as Computer-Aided Design (CAD) tools, Application Specific Integrated Circuit (ASIC) CAD tools, VHDL editors, Verilog editors, or the like. These tools, however, are unable to perform certain processing functions on cyclic circuit designs. These functions may include, but are not limited to: timing optimization processes, element sizing, layout, signal routing, and so on. Rather, the tools may be capable of performing these functions only on acyclic circuit designs that can be represented as a directed acyclic graph (DAG). Accordingly, what is needed are systems and methods for cutting cycles in cyclic circuits so they can be represented as a DAG and be correctly processed by CAD tool flows.